Đề tài A soft error tolerant sram design in 130nm cmos technology - Lê Thị Linh An

VIETNAM NATIONAL UNIVERSITY – HO CHI MINH CITY UNIVERSITY OF SCIENCE LÊ THỊ LINH AN A SOFT ERROR TOLERANT SRAM DESIGN IN 130NM CMOS TECHNOLOGY Specialization: Electronic Engineering – Microelectronics Major Code: 60 52 70 MASTER DEGREE THESIS ELECTRONICS ENGINEERING – MICROELECTRONICS SUPERVISOR Dr. BÙI TRỌNG TÚ Ho Chi Minh City, 2010 ACKNOWLEDGEMENTS It is my pleasure to thank all the people who made this thesis possible. First of all, I would like to sincerely express my appreciation to my advisor, Dr. Bui Trong Tu, for his tremendous support, valuable guidance and constant encouragement during my studies. His technical advice made my master’s studies a meaningful learning experience. I am also grateful to Prof. Dang Luong Mo, Prof. Nguyen Huu Phuong, and Dr. Huynh Huu Thuan, who are the managers of this Microelectronics Master program. This is really an interesting course with enthusiastic and devoted professors, who are the experts in the IC industry. I also wish to thank my colleagues in TCAM team for all helpful discussion and valuable advice during my study. Appreciation is expressed for Silicon Design Solutions Company who have supported me about financial and let me join in this Master course during my work. Finally, my special thanks to my family who have always been with me throughout the difficulties and challenges of my master study. Ho Chi Minh City, November 2010 Le Thi LinhAn ABSTRACT Soft error is a great concern for microelectronics circuits today. With the advanced development in CMOS technologies, VLSI circuits are becoming more sensitive to external noise sources, especially radiation particle strikes, which are the cause of soft error. Soft errors are random and do not cause the permanent failure. However, it causes the corruption of stored information, which could turn to the failure in functionality of the circuits. Meanwhile, the demand for a higher reliability of electronics applications is always a non-stop requirement. There are a lot of critical applications that need the extreme exactly in circuit functionality, such as the circuits used in space or biomedical equipment, as well as the military electronics and so on. Generally, soft errors in memories attracted more attention than soft errors in logic circuit. In addition, memories play an important part in modern system. Because of the high integration of storage cells, a large memory is more sensitive to particle strikes than logic. Due to that motivation, this thesis focuses to study about soft errors in memories. The thesis goes through the background knowledge of soft errors and its mitigation techniques. Then, a SRAM design with additional soft error tolerant feature will be presented. The SRAM is designed in 130nm CMOS technology, using circuit hardening and error correcting code techniques to mitigate the soft error effect. The soft error tolerant level is verified by some simulations. Not only focus on the soft error tolerant circuits, a whole SRAM architecture will be shown in detail, from circuit to physical implementation. The verification and simulation results are also included. TABLE OF CONTENTS Acknowledgement Abstract Table of contents Abbreviations List of tables List of figures CHAPTER 1 - INTRODUCTION .................................................................................... 1 1.1. Problem and motivation ............................................................................................. 1 1.2. Contribution of the thesis ........................................................................................... 2 1.3. Thesis organization .................................................................................................... 2 CHAPTER 2 - BACKGROUND ....................................................................................... 4 2.1. Soft errors in semiconductor device ........................................................................... 4 2.1.1. Radiation sources ................................................................................................. 4 2.2. Soft errors occurrence mechanism ............................................................................. 5 2.3. Soft errors mitigation techniques ............................................................................... 6 2.3.1. Device level techniques ....................................................................................... 6 2.3.2. Circuit level techniques ....................................................................................... 7 2.3.3. Block level techniques ......................................................................................... 7 CHAPTER 3 – SOFT ERROR TOLERANT SRAM DESIGN ................................... 10 3.1. SRAM specification ................................................................................................. 10 3.1.1. General information ........................................................................................... 10 3.1.2. Floorplan ............................................................................................................ 11 3.1.4. Operation brief description ................................................................................ 12 3.2. SRAM detail design ................................................................................................. 14 3.2.1. SRAM cell architecture ..................................................................................... 14 3.2.2. Replica path for Read operation ........................................................................ 15 3.2.3. Internal clock generator ..................................................................................... 17 3.2.4. Write circuit ....................................................................................................... 19 3.2.5. Decoder .............................................................................................................. 19 3.2.6. Input/output latches .......................................................................................... 21 3.3. Error detecting and correcting (EDC) block ............................................................ 22 3.3.1. Hamming code algorithm .................................................................................. 23 3.3.2. EDC block implementation ............................................................................... 24 3.3.3. EDC detail architecture ...................................................................................... 26 CHAPTER 4 – DESIGN SIMULATION AND VERIFICATION .............................. 37 4.1. SRAM cell simulation .............................................................................................. 37 4.1.1. SRAM cell simulation to find device size ......................................................... 37 4.1.2. SRAM cell characteristic summary ................................................................... 42 4.1.3. Static noise margin comparison ......................................................................... 43 4.1.4. SRAM cell capacitance ...................................................................................... 43 4.2. Soft error tolerant simulation ................................................................................... 44 4.2.1. Verification methodology .................................................................................. 44 4.2.2. Critical charge simulation .................................................................................. 45 4.2.3. Simulation results .............................................................................................. 46 4.2.4. Conclusion ......................................................................................................... 49 4.3. Post-layout simulation .............................................................................................. 50 4.3.1. Simulation setup ................................................................................................ 50 4.3.2. Cycle time definition and simulation result ....................................................... 52 4.3.3. Access time ........................................................................................................ 55 4.3.4. Setup time .......................................................................................................... 56 4.3.5. Timing delay of some critical paths................................................................... 57 4.3.6. Simulation results summary .............................................................................. 61 4.4. SRAM and EDC functional verification .................................................................. 61 4.4.3. Simulation setup ................................................................................................ 65 4.4.4. Functional verification result ............................................................................. 67 4.5. Physical verification ................................................................................................. 70 CHAPTER 5 – CONCLUSION AND FUTURE WORK ............................................. 75 ABBREVIATIONS VLSI Very large scale integration CMOS Complementary Metal-Oxide Semiconductor SEU Single Event Upset DRC Design Rule Check LVS Layout versus Schematic SRAM Static Random Access Memory ECC Error Correcting Code EDC Error Detecting and Correcting SNM Static noise margin LPE Layout Parasitic Extraction LIST OF TABLES Table 3.1: Pin description ................................................................................................... 12 Table 3.2: Hamming code for 22 bits ................................................................................. 24 Table 4.1: Read current ...................................................................................................... 38 Table 4.2: Read leakage current ......................................................................................... 38 Table 4.3: Effect of leakage on read current ...................................................................... 38 Table 4.4: Write current ..................................................................................................... 40 Table 4.5: Static noise margin ............................................................................................ 41 Table 4.6: SRAM cell characteristic summary .................................................................. 43 Table 4.7: SNM comparison ............................................................................................... 43 Table 4. 8: SRAM cell capacitance .................................................................................... 44 Table 4.9: Critical charge result of hardened SRAM cell .................................................. 46 Table 4.10: Critical charge result for normal SRAM cell .................................................. 48 Table 4.11: Performance result (SS_125_1.35) ................................................................. 61 Table 4.12: Timing delay between nodes ........................................................................... 61 Table 4.13: Design fault model .......................................................................................... 62 LIST OF FIGURES Figure 2.1: Redundancy ........................................................................................................ 8 Figure 2.2: Concurrent error detection ................................................................................. 8 Figure 3.1: SRAM floorplan ............................................................................................... 11 Figure 3.2: Write operation ................................................................................................ 13 Figure 3.3: Read operation ................................................................................................. 13 Figure 3.4: SRAM cell architecture .................................................................................... 15 Figure 3.5: Timing scheme for read operation ................................................................... 16 Figure 3.6: Reference IO cell and read circuit ................................................................... 17 Figure 3.7: Read clock generator circuit ............................................................................ 18 Figure 3.8: Write clock generator ....................................................................................... 19 Figure 3.9: Write circuit and sequential waveform ............................................................ 19 Figure 3.10: Row decoder block diagram .......................................................................... 20 Figure 3.11: Xdec circuit .................................................................................................... 21 Figure 3.12: Hardened latch architecture ........................................................................... 22 Figure 3.13: EDC block diagram ........................................................................................ 25 Figure 3.14: Write encoder schematic ................................................................................ 27 Figure 3.15: Parity comparison schematic ......................................................................... 28 Figure 3.16: Syndrome decoder schematic ........................................................................ 29 Figure 3.17: Bit flipper block ............................................................................................. 30 Figure 3.18: Input select ..................................................................................................... 31 Figure 3.19: Output select and output latch........................................................................ 32 Figure 3.20: Top level layout view ..................................................................................... 33 Figure 3.21: SRAM cell layout with only device layers shown ......................................... 34 Figure 3.23: Xdec cell layout ............................................................................................. 34 Figure 3.22: SRAM cell layout .......................................................................................... 34 Figure 3.24: Xdec array 1x256 ........................................................................................... 35 Figure 3.25: Control block .............................................................................................. 35 Figure 3.26: IO array 1x22 ................................................................................................. 36 Figure 4.1: Read current ..................................................................................................... 37 Figure 4.2: Write current .................................................................................................... 39 Figure 4.3: Inject a current source to an off NMOS drain ................................................. 45 Figure 4.4: The injected SEU current for hardened SRAM cell ........................................ 47 Figure 4.5: IBL waveform of hardened SRAM cell ........................................................... 47 Figure 4.6: The exchange state between IBL and IBLX .................................................... 47 Figure 4.7: The injected SEU current for normal SRAM cell............................................ 48 Figure 4.8: IBL waveform of normal SRAM cell .............................................................. 48 Figure 4.9: The exchange state between IBL and IBLX .................................................... 49 Figure 4.10: A part of LPE netlist containing capacitance value ....................................... 50 Figure 4.11: A part of LPE netlist containing resistor value .............................................. 51 Figure 4.12: A part of input waveform for performance simulation .................................. 51 Figure 4.13: Hspice option ................................................................................................. 52 Figure 4.15: Delay from clk rise to resetx rise ................................................................... 53 Figure 4.14: Cycle time must cover the internal clock ....................................................... 53 Figure 4.17: Delay from clk rise to dmrbl rise ................................................................... 54 Figure 4.16: Cycle time must make sure all RBL be precharged fully .............................. 54 Figure 4.18: Cycle time must cover PWH of input latch plus for max setup time ............ 55 Figure 4.19: PWH of input latch ........................................................................................ 55 Figure 4.20: Access time definition.................................................................................... 56 Figure 4.21:Access time ..................................................................................................... 56 Figure 4.22: Address input path delay ................................................................................ 57 Figure 4.23: Clock path delay ............................................................................................ 57 Figure 4.24: Delay from CLKA to intckx fall .................................................................... 58 Figure 4.25: Delay from intclk fall to rhcpx fall ................................................................ 58 Figure 4.26: Delay from rhcpx fall to latch rise ................................................................. 58 Figure 4. 27: Delay from rhcpx fall to echo rise ................................................................ 59 Figure 4.28: Delay from echo rise to resetx fall ................................................................. 59 Figure 4.29: Delay from resetx fall to intclk rise ............................................................... 59 Figure 4.30: delay from intclk rise to rhcpx rise ................................................................ 60 Figure 4.31: Delay from rhcpx rise to latch fall ................................................................. 60 Figure 4.32: Delay from intclk rise to resetx rise ............................................................... 60 Figure 4.33: Netlist of top level .......................................................................................... 66 Figure 4.34: A part of full test vector ................................................................................. 66 Figure 4.35: Hsim option .................................................................................................... 67 Figure 4.37: Waveform of SRAM functional simulation ................................................... 68 Figure 4.36: Hsim log file .................................................................................................. 68 Figure 4.38: Waveform of EDC functional simulation ...................................................... 69 Figure 4.39: LVS Calibre report for hierachical checking ................................................. 71 Figure 4.40: Detail LVS report for top level ...................................................................... 72 Figure 4.41: DRC report ..................................................................................................... 74 CHAPTER 1 INTRODUCTION P a g e | 1 CHAPTER 1 INTRODUCTION 1.1. Problem and motivation Reliability is the key challenge facing the modern VLSI system. The advanced development of CMOS technologies has resulted in the lower supply voltages, higher clock frequencies, and the increasing of transistor integration densities. Consequently, VLSI circuits are becoming more vulnerable to various noise sources. It can be listed here some well-known noise effects such as: the power and ground noise, capacitive coupling noise, radiation particle strikes … With the rapid scaling of technology, integrated circuits (ICs) are turned to be very sensitive to the radiation particles strikes. When a radiation particle strike at a sensitive region in a semiconductor device, the charges generated could corrupt the stored information in the memory element, resulting in an erroneous data at the output, or so called soft error. Soft errors are incidental and do not destroy the device. They just cause the temporary functional failure and the system still works well after that. The radiation particle striking is a random natural phenomenon; therefore they cannot be predicted or controlled by the designers. The charge particles could be the alpha particles, neutron induced 10B fission and high energy cosmic ray neutrons. The source of charge particles can be from the radioactive material or cosmic rays. In addition, it could also be the result of high energy particle interaction with semiconductor itself. Electronics applications nowadays always require a higher reliability level. Many critical applications such as biomedical circuits, as well as space and military electronics devices demand extreme high reliable circuit functionality. That means soft errors are becoming more and more unacceptable, even in the commercial CHAPTER 1 INTRODUCTION P a g e | 2 applications [1]. Therefore, soft error elimination is a major consideration of all VLSI circuits today. Memories always have a high density integration of storage elements. Hence, they are more sensitive to soft errors than in logic circuit. The soft errors in memories (SRAM and DRAM) were widespread studied from the end of the twentieth century [2]. However, it is still problematic up to now. Due to that motivation, this thesis focuses to study the soft errors on memories (specific in SRAM) and applies some mitigation techniques to design a SRAM with soft error tolerant feature. 1.2. Contribution of the thesis The thesis presents the detail design of a synchronous two-port SRAM in 130nm CMOS technology, with additional soft error tolerant feature. The design was applied two soft error mitigation techniques; those are circuit hardening and error correcting code (ECC) techniques. For the first technique, only some special parts of the design are selected to be hardened. They are the memory cell, the address input latches, data input and output latches, keeper circuits… These are parts that most easily suffer from soft error of a memory because they are storage elements. The second technique helps to recover the design if unfortunately the soft error occurred. It is a built-in error detecting and correcting (EDC) block for the SRAM. This block was applied the ECC techniques, used the Hamming code to detect if there is a single bit or double bit error in a memory array. And it will also function as a correcting circuit if there is a single bit upset. 1.3. Thesis organization The rest of thesis is organized as follows: Chapter 2 introduces the background knowledge of soft error, its mechanism as well as the mitigation techniques. CHAPTER 1 INTRODUCTION P a g e | 3 Chapter 3 describes detail about the SRAM design, including the SRAM specification, SRAM architecture, specific design for soft error tolerant feature and the physical implementation. Chapter 4 focuses on the verification methodologies and the simulations result. These simulations include the soft error tolerant level simulation, memory cell characteristic, post layout simulation, functional verification and physical verification. Finally, chapter 5 shows the conclusion and some discussions to improve this SRAM design. CHAPTER 2 BACKGROUND P a g e | 4 CHAPTER 2 BACKGROUND 2.1. Soft errors in semiconductor device Soft errors, also called Single Event Upset (SEU), are the errors in microelectronics circuit caused when the radiation particles strike at sensitive regions of the silicon devices. Soft errors are incident and no breakage of the device occurs [3]. They only flip the stored state of a memory element and will generate an erroneous value at output. Soft errors cause no permanent faults; the system still work well after suffering from an SEU. Therefore, they are named as soft error. This background section will help to get an overview of radiation sources which are the cause of soft errors and the mechanism of soft errors occurrence in semiconductor devices. 2.1.1. Radiation sources Radiation is kinetic energy in the form of high speed particles and electromagnetic waves [4]. Typically, three main sources of radiation causing soft errors in semiconductor device could be summarized as following: · Alpha particles: are the nuclei of helium atoms consisting of 2 protons and 2 neutrons. Alpha particles are generated from the radioactive decay process and when they collide with other atoms. Because of alpha particles cannot travel a long path in material, atmosphere therefore is not the main source of alpha particles, but an integrated circuit itself. Packaging and soldering contain traces of radioactive isotopes, which lead to release the alpha particles as well as other particles such as gamma and beta particles, as they decay to lower state. Alpha particles contain the kinetic energy in the range of 4 to 9 MeV [5] CHAPTER 2 BACKGROUND P a g e | 5 · High energy neutrons: when the cosmic radiation reacts with the atmospheres, it will cause the generation of secondary particles, includes protons, electrons, neutron … All of them can cause soft errors; however, charge generation property of neutron for the same energy is more than proton or electron. Neutron does not contain charge; therefore, the ionization in material cannot be caused by itself. However, when a neutron with energy above 1 MeV interacts with the silicon atoms, it will cause a nuclear reaction which generates charged particles. These charged particles cause ionization, lead to the soft error in the device. · Thermal neutrons: thermal neutrons are low energy neutrons with a kinetic energy of about 0.025 eV. The interaction of low energy cosmic neutrons and doping boron (isotope 10B and 11B) in semiconductor material generates the secondary radiation particles (the lithium atom and alpha particle). Both these particles can cause soft errors in the device 2.2. Soft errors occurrence mechanism In semiconductor device, there are some sensitive nodes which are easily to suffer from SEU. Those are the drain of the off NMOS and off PMOS transistors. Consider an off NMOS transistor, its source, gate and substrate terminals are connected to VSS. The drain is connected to VDD. The drain and substrate of this OFF transistor form a reverse-biased junction. Therefore, a strong electric field from drain to substrate exists in the depletion region of this junction. Because radiation particles generate the free electron hole pairs, this electric field will cause the collection of electron at drain and of hole at the substrate. That’s why these reverse-biased junctions are the most sensitive nodes to the particle strikes. When the particles strike at these sensitive nodes, due to the electric field of the reversed-biased junction, the generated charges are collected at the opposite voltage terminals (drain and substrate) of the reverse-biased junction. Electrons move towards the positive voltage while holes move toward the negative voltage. CHAPTER 2 BACKGROUND P a g e | 6 This event will cause a current pulse, flow from the n type diffusion to the p type diffusion in a very short duration. When the charge collection exceeds the critical charge, the storage value will be changed. Critical charge (Qcrit) is the minimum charge required to flip the cell. The Qcrit depends on the characteristic of the circuit, especially the supply voltage and the nodal capacitance of the drain [6]. When a particle strike discharges the charge stored at the drain of the OFF-NMOS transistor, it will flip from 1 to 0. Similarly for a 0 to 1 flip when it strikes the drain of the OFF-PMOS transistor. As technology scales down, to adapt the higher requirement for constraining the power and making the circuit transient faster, the supply voltage and nodal capacitance is decreasing swiftly. That makes the charge stored at the sensitive nodes of the device is reduced because Qnode = Cnode×Vdd, resulted in the more and more vulnerable to soft errors of SRAM. 2.3. Soft errors mitigation techniques In general, the soft error mitigation techniques could be classified into three categories: device level techniques, circuit level techniques and block level techniques 2.3.1. Device level techniques At this level, some methods were given out to edit the traditional fabrication process to make the device resistant to soft error. The manufacturers and designer could choose the appropriate material, package, as well as the better device geometries. For example, soft errors can be caused by alpha particles which are emitted by the materials or compounds used in packaging. Therefore, choosing the appropriate material which has the less probability of alpha particles could minimize the soft error rate. Or to reduce the soft error induced by the interaction of low energy cosmic neutrons and doping boron CHAPTER 2 BACKGROUND P a g e | 7 10B, BPSG (boron phosphor silicate glass) is replaced by other insulators that do not contain boron. 2.3.2. Circuit level techniques The technique that is mostly used at this level to make the circuit resistant to SEU is radiation hardening technique [7]. With this technique, some special parts of the design are chosen to be hardened. Basic circuits element such as Inverter, Nand, Nor, flip-flop or latches are made SEU resistant by adding extra transistor than normal. Normally, this technique is often applied to the memory cell, keeper circuits, latches or flip-flops which are data storage element, thus are easily suffer from soft errors. It will help to increase the critical charge at sensitive nodes, making those nodes less susceptible to the SEU. This technique is widely used because the designer can predict which nodes are sensitive to protect them from the SEU. However, this technique causes the overhead in area and power consumption [8]. 2.3.3. Block level techniques Different with two approaches above, the block level techniques are used to detect the error and recover the design after being suffered from SEU, while the two approaches above mainly protect and enhance the design. There are two main mitigation techniques at this level: 2.3.3.1. Redundancy The redundancy techniques often clone to create the redundant circuit. However, this result the area and performance overhead, also higher power consumption. Triple modular redundancy is a classical method which has the high soft error reliability. Three identical copies of a circuit compute on the same data in parallel. The three outputs are then evaluated CHAPTER 2 BACKGROUND P a g e | 8 by the majority voting logic. It will return the value that occurred in at least two of three cases. By using this technique, the soft error will be detected if it occurs at one of the three circuits, assuming the other two circuits operated correctly. Figure 2.1: Redundancy Another example of redundancy is using concurrent error detection, from which, only a selected parts of the design are chosen to be duplicated. Figure 2.2: Concurrent error detection In these techniques, selecting the parts to be duplicated is very important. If the particle strike happens in the non-duplicated region, it cannot be detected. In contrast, if it occurs at the duplicated portion of the circuit, the checker could detect it. Therefore, must be careful to select the cutset logic in which the nodes have highest soft error susceptibility [9]. 2.3.3.2. Error correcting code and parity CHAPTER 2 BACKGROUND P a g e | 9 Due the soft error doesn’t destroy the device, if soft errors occur, we can remove them by rewriting the correct data to it, or we can get the correct output data by fixing the error bits before it comes to the output. This technique incorporates redundant data into each word to create an error correcting code (ECC), which used to detect and correct the soft error [10]. Normally, the redundant data are the parity bits generated during write operation. These parity bits are stored in memory array. Each time to data is read, they will be used to detect the error and correct the error bit. Used ECC can be Hamming code, Turbo code … CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 10 CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN 3.1. SRAM specification 3.1.1. General information · Two-ports synchronous SRAM 22kbit memory · Built-in Error Detecting and Correcting (EDC) block to mitigate soft error. The EDC block could detect single bit/double bit error and only fix single bit error. · This SRAM was designed in 130nm CMOS technology. · Operating voltage range is from 1.35V to 1.65V · Operating frequency is 200MHz (at worst case) · Hand-crafted layout · 22 bit data in/out for SRAM · Only 16 bit data in/out for EDC block interface because the remaining 6 bit data of SRAM were used as parity bit check. · 8 row addresses input and 2 column addresses IO · Two independent clocks for read and write operations as well as two independent data in/out ports and address buses. · Some parts of the design were selected to be radiation hardened · There is also the memory enable control for read and write. · EDC enable pin allows to operate with or without error detection and correction task CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 11 3.1.2. Floorplan MEMORY ARRAY R E F C O L U M N ROW DECODER CONTROL BLOCK R E F I O C E N A REF ROW BUILT-IN EDC BLOCK C E N B A A [0 :9 ] A B [ 0 :9 ] C E N A C E N B C E N A C E N B A A [0 :9 ] A B [ 0 :9 ] C E N A C E N B BUILT-IN EDC BLOCK Q A [0 :2 1 ] D B < 0 :2 1 ] B W E N L A T C H Q I[ 0 :2 1 ] Q I[ 0 :2 1 ] R A M _ M O D E L A T C H S E D E P E R A M _ M O D E D I< 0 :1 5 ] Q O [0 :1 5 ] A B [ 0 :9 ] A A [0 :9 ] C E N B C E N A C E N B C E N A COLUMN MUX SENSE AMPLIFIER - OUTPUT BUFFER Figure 3.1: SRAM floorplan CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 12 3.1.3. Interface pin description Table 3.1: Pin description Pin Name Description CLKA Read port clock input CLKB Write port clock input CENB Write enable CENA Read enable AA Read address AB Write address DI Data in QO Data output RAM_MODE EDC block disable pin · RAM_MODE = 0: the SRAM will work with error detecting and correcting tasks · RAM_MODE = 1: the SRAM will work in normal mode, without error detecting and correcting tasks. DE Double bit error flag SE Single bit error flag PE Parity bit error flag 3.1.4. Operation brief description 3.1.4.1. SRAM operation A write operation is started at the rising edge of CLKB signal. The write enable control input, data input and address input are latched at the beginning of each cycle. During a write operation, data will be written into the memory, and the data will not propagate to the memory output. CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 13 The memory output will remain at the value determined by the last memory read. Figure 3.2: Write operation Similarly, a read operation is started at the rising edge of CLKA signal. The read enable control input and address input are latched at the beginning of each cycle. The data output latch is latched following each read access, controlled by the track path. Figure 3.3: Read operation 3.1.4.2. Built-in EDC operation In each write operation, the 16 bit data input DI of EDC will be encoded to 6 parity bits following the Hamming code. After that, 16 bit data input and 6 parity bits will propagate to 22-bit data in ports DB of the SRAM. That means, in the memory array, only 16 bit is CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 14 data information, the other 6 bits contain the error correcting code, which used to detect and fix the data information if there are errors. In each read operation, the 22 bit data output from SRAM QAwill propagate to the QI of EDC block. EDC will decode 16 bit data output read from the SRAM to six check bits. These six checked bit will be compared with the parity bits read from the memory. If single bit error occurred, EDC would detect and fix. The SE flag will be on and the data output is correct data. If double bit error occurred, EDC would detect but not fix. The DE flag will be on to indicate there is a double bit error. The detail functional of the EDC block will be discussed in EDC architecture section. 3.2. SRAM detail design 3.2.1. SRAM cell architecture This SRAM cell was applied the circuit hardening technique [11, 12]. Some extra transistors were adding to the classic 8 transistors SRAM cell. In detail, two additional inverters and a control transistor are included as in figure below. The control transistor is ON when both RWL and WWL are low. Therefore, this extra protection circuit is only turned on in standby mode. During the standby mode, the extra transistors will be used to enhance the charge value of IBL and IBLX, which lead to increase the critical charge value of these nodes. That means, the soft error tolerant level of this SRAM cell is improved. The level of soft error tolerant depends a lot on the physical parameter and characteristic of the extra transistors. CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 15 Figure 3.4. SRAM cell architecture Because the protection circuit is OFF during normal mode (read/write), it will not affect a lot the read and write performance. The level of soft error tolerant depends a lot on the physical parameter and characteristic of the extra transistors. Increasing width of extra transistor could enhance the tolerance level; however, this will trade off with the area overhead. 3.2.2. Replica path for Read operation WWL WWL RWL RWL PENX PENX WBL WBL RBL RBL WBLX WBLX IBLX IBL Figure 3.4: SRAM cell architecture CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 16 This design uses the inverter sense; the output latch is enabled by the signal obtained from the reference column and reference row. Reference column is an additional column used to generate the enabling signal for the output latch. It has 256×1 bits and the same bitline capacitance as that in the cell array. Reference row is an additional row used to generate the reference read wordline signal which reads the cells in reference column. This additional row makes the reference read wordline have the same capacitance as that for wordlines in cell array. The reference row and column are configured to model the furthest path of the array. Therefore, ensure that the output latch is opened after the data read from memory valid. The reference column cell, reference row cell, reference feedback row cell are the edition of the memcell. In the reference column cell, the “pull up” pmos transistors are disconnected from the IBL because these cells are just used to model the bitline capacitance. In the reference row cell, IBL, IBLX and DMWWL are shorted together while DMWWL is tied to VSS at XDEC block. The reference feedback row cell is put at the middle of the array. The DMRWLFB signal is enabled when DMRWL reaches to the feedback cell. In the reference memcell, IBL and IBLX are tied to high. DMXDEC XDEC CTL XDEC REFMEM REFROW REFROWFB REFROW … … … REFCOL MCELL MCELL MCELL … … REFCOL MCELL MCELL MCELL … … … IOREF IO IO IO CPGEN VC P LATCH DMRWL DMRWLFB D M RB L ECHO CLKA Out latch Out latch Out latch QA[0] QA[21] QA[n] Figure 3.5: Timing scheme for read operation CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 17 During the read operation, both the accessed RWL and the reference RWL go high. The reference_row_feedback cell enables the DMRWLFB, leads to a read 0 operation at the reference memcell. The DMRBL is discharged, opens the output latch, and also sends the echo signal back to reset internal clock. Figure 3.6 above shows the schematic of reference IO cell and the read circuit in IO cell. In the cycle low, the DMRBL is pre-charged. When the read operation is initiated, a read 0 from reference memcell will discharge the DMRBL. Therefore, send the signal to open the output latch of the read circuit in the IO cells, the read data then propagate to output port. The output latch is closed by the falling edge of internal read clock to keep the value of data out. 3.2.3. Internal clock generator 3.2.3.1. Read clock generator circuit LATCH Mux select RMSE RMSE RB L< 0: 3> RHCPX Output latch Figure 3.6: Reference IO cell and read circuit CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 18 A read operation is starting by the rising edge of CLKA. Signal PULDOWN is delayed from CLKA to pull the INTCLKX down to VSS. Rising edge on LCP pulse is sent to IO block to start a read operation. As mention in the 3.2.2 section, when the DMRBL is discharged, an echo signal will be sent back to read clock generator circuit, indicate that the high level duration of read clock is enough for a read operation, then the LCP signal will be reset (RESETX goes low). This will be sent to the IO block to close the output latches. After when the LCP is reset, the feedback signal (HCPFB) will come back to disable the reset signal (RESETX goes high). Then it is ready to start a new read cycle. HCPFB RESETX Figure 3.7: Read clock generator circuit CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 19 3.2.3.2. Write clock generator circuit There are two main control pulses generated from write clock generator circuit. One is the WVCP which goes to XDEC block to open the WWL. The other is WHCPX which goes to IO block to control the write operation. 3.2.4. Write circuit Figure 3.9 below is the write circuit and its sequential waveform. The data will be written to the memory array when both write clock (WCP) and mux select (WMSE) enable. A write 0 operation will pull down the WBL while a write 1 will pull down the WBLX. Both the read and write circuit are included in the IO cell. e 3.2.5. Decoder · Row Decoder Figure 3.9: Write circuit and sequential waveform Figure 3.8: Write clock generator CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 20 An 8-256 decoder which decodes the higher 8 address inputs (A2-A9) to select the accessed row. There are two decoding outputs for each row, Write WordLine (WWL) and Read WordLine (RWL), active during write and read operation respectively. The decoder is implemented as following block diagram to improve area and performance. Figure 3.11 below shows the circuit of XDEC bloc. The TGATE is enabled when this row is selected by the 2_to_8 decoder. When the read or write control pulse goes high (RVCP/WVCP), the read or write word line will be opened. The PENX which enable the protection circuit in SRAM cell will go low (PENX active low) when both RWL and WWL is disabled. 2_dec_4 A< 2> A< 3> PA 0 PA 1 PA 2 PA 3 2_dec_4 A< 4> A< 5> PB 0 PB 1 PB 2 PB 3 2_dec_4 A< 6> A< 7> PC 0 PC 1 PC 2 PC 3 2_dec_4 A< 8> A< 9> PD 0 PD 1 PD 2 PD 3 WWL RWL XDEC_0 PA0 PB0 PC0 PD0 A B C D WWL RWL XDEC_1 PA1 PB0 PC0 PD0 A B C D WWL RWL XDEC_255 PA3 PB3 PC3 PD3 A B C D ..… Figure 3.10: Row decoder block diagram CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 21 The TGATE is enabled when this row is selected by the 2_to_8 decoder. When the read or write control pulse goes high (RVCP/WVCP), the read or write word line will be opened. The PENX which enable the protection circuit in SRAM cell will go low (PENX active low) when both RWL and WWL is disabled. · Column Decoder: A 2-4 decoder which decodes the lower 2 address inputs (A0-A1) to select the accessed column. 3.2.6. Input/output latches Just like the SRAM cell, the latches are parts that easily suffer from SEU. Latches are used at address input, data input and data output. Opening latch will let data go through, however, when closed; data will be stored in latch. A SEU could flip the state of data stored in latch, lead to an erroneous data. Therefore, in this SRAM design, latches are hardened to duplicate some sensitive nodes. All the latches in the design, include address input latch, data input latch and output latch are applied this techniques. WWL RWL PENX Figure 3.11: Xdec circuit CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 22 Figure 3.12: Hardened latch architecture The hardened latch architecture is shown in the figure 3.12 above. In this latch architecture, each sensitive node is strengthened by adding more transistors. For example, node DX1 is the duplication of node DX2. This is done by the two additional transistors, N2 and P2, similarly for node Q1 and Q2. So, if a SEU occurred at the DX2 branch, then the data will be saved by the DX1 branch. The feedback circuit which is enabled when closing latch is also divided in two, the above one is used to feedback the ‘1’ value while the below one is used to feedback the ‘0’ value. With this latch architecture, the soft error tolerant level could be increased significantly. 3.3. Error detecting and correcting (EDC) block The EDC block used the Hamming code algorithm[10, 13] to implement the error correcting code. The EDC block encodes all data bits into parity bits to be written N2 P2 Q1 Q2 CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 23 into memory during write operation. During the read operation, it evaluates these parity bits to detect if the data bits are erroneous. For single bit error detected, EDC can flag and correct while it can only flag if there is a double bit error. 3.3.1. Hamming code algorithm Do the following step to have a visual view about the Hamming code algorithm: · Step 1: Number the bits starting from 1: bit 1, 2, 3, 4, 5, etc. · Step 2: Write the bit numbers in binary. 1, 10, 11, 100, 101, etc. · Step 3: All bit positions that are powers of two (have only one 1 bit in the binary form of their position) are parity bits. · Step 4: All other bit positions, with two or more 1 bits in the binary form of their position, are data bits. · Step 5: Each data bit is included in a unique set of 2 or more parity bits, as determined by the binary form of its bit position. o Parity bit P0 covers all bit positions which have the least significant bit set: bit 1 (the parity bit itself), 3, 5, 7, 9… o Parity bit P1 covers all bit positions which have the second least significant bit set: bit 2 (the parity bit itself), 3, 6, 7, 10, 11, … o Parity bit P2 covers all bit positions which have the third least significant bit set: bits 4–7, 12–15, 20–23 … o Parity bit P3 covers all bit positions which have the fourth least significant bit set: bits 8–15, 24–31, 40–47 … o Parity bit P4 covers all bit positions which have the fifth least significant bit set: o The parity bit P5 is the special bit which covers all bit position, the purpose is to distinguish the error is single bit or double bit Following table is the example of 22 encoded bits which were applied for 22k SRAM. CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 24 Table 3.2: Hamming code for 22 bits Bit position Bit position in binary Encoded data bits Parity bit coverage P0 P1 P2 P3 P4 P5 1 001 P0 x 2 010 P1 x 3 011 D0 x x x 4 100 P2 x 5 101 D1 x x x 6 110 D2 x x x 7 111 D3 x x x x 8 1000 P3 x 9 1001 D4 x x x 10 1010 D5 x x x 11 1011 D6 x x x x 12 1100 D7 x x x 13 1101 D8 x x x x 14 1110 D9 x x x x 15 1111 D10 x x x x x 16 10000 P4 x 17 10001 D11 x x x 18 10010 D12 x x x 19 10011 D13 x x x x 20 10100 D14 x x x 21 10101 D15 x x x x It can be seen from the table that any given data bit is included in a unique set of parity bits. To check for errors, check all of the parity bits. The parity bit P5 will indicate whether it is a single or double bit error. The remaining parity bit will determine the bit position if it is a single bit error. For example, D0 is included in the unique set of P0 and P1, so if D1 is the erroneous bit, then the parity bit P5, P0 and P1 value will be different with the original. Parity P5 shows that there is a single bit error and P0 and P1 identify the erroneous bit is D0. 3.3.2. EDC block implementation CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 25 3.3.2.1. Block diagram 3.3.2.2. EDC operation using Hamming code algorithm The Hamming code algorithm is implemented for 22 k SRAM as following: · During the write operation, 16 data input bit are encoded to 6 parity bits P by XOR operator with the checkpoint in the table 3.2. Then the W RI TE E N CO D ER RE A D D EC O D ER P AR IT Y CO M PA RA TO R SY N D RO M E D EC O D ER BI T FL IP PE R EDC BLOCK DI <0 :1 5> P< 0: 5> D I< 0: 15 > D E PE SE Q O <0 :1 5> Q I< 0: 21 > Q I< 0: 15 P< 0: 5> Q I< 0: 15 > Q I< 16 :2 0 > Q I< 16 :2 1 > P< 0: 5> PD PO FEN D I< 0: 21 > READ and PARIRY DECODER Q I< 0: 15 > D< 0: 15 > O U TP U T SE LE CT O U TP U T SE LE CT Q <0 :1 5> LATCH LATCH VSS RAM_MODE RAM_MODE RA M _M O DE RA M _M O DE LA TC H Figure 3.13: EDC block diagram CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 26 total 22 bit (data and parity bits) are written to the memory array (the six right bits of the memory array used to store the parity bit information) · During the read operation, 16 data output bit will be decoded to 6 check bits PD by XOR operator like in write operation. Note that the PD is the XOR operation of all data output bit and parity bit P read from memory. · Compare P and PD by XOR operator: PO = XOR{P, PD} o If PO = 1, single bit error occurred, SE flag will be ON § If PO=0, the single bit error is one of the parity bit from P0 to P4. The PE flag will be ON § Otherwise, the single bit error is one of the data bit. The error bit position is determined by equation Error Bit position = PO x 24 + PO x 23 + PO x 22 + PO x 21+ PO x 20 o If PO = 0 and PO result in a non zero value, then the double bit error occurred, DE flag will be on o If single bit error occurred, the error bit will be flipped. o If P = 0, there are no error. 3.3.3. EDC detail architecture 3.3.3.1. Write encoder The write encoder block uses the XOR operation to encode 16 data bit inputs to six parity bits following the Hamming code algorithm CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 27 Following the Hamming code algorithm in table 3.2, the parity bits are encoded as below: P0 = XOR{ D0, D1, D3, D4, D6, D8, D10, D11, D13, D15} P1 = XOR{ D0, D2, D3, D5, D6, D9, D10, D12, D13} P2 = XOR{ D1, D2, D3, D7, D8, D9, D10, D14, D15} P3 = XOR{D4, D5, D6, D7, D8, D9, D10} P4 = XOR{D11, D12, D13, D14, D15} P5 = XOR{D, P} 3.3.3.2. Read decoder The read decoder decodes 16 data output to 6 check bits PD by XOR operator like in write encoder. Note that the PD is the XOR operation of all data output bit and parity bit P read from memory, which are now the QI output from the memory. Please refer to figure 3.13. The read decoder schematic is also similar to the write encoder schematic. D0, D1, D3, D4, D6, D8, D10, D11, D13, D15 SRAM_XOR10 D Y P0 SRAM_XOR7 D Y P3 D D0, D2, D3, D5, D6, D9, D10, D12, D13 SRAM_XOR9 D Y P1 SRAM_XOR5 D Y P4 D D, D, D SRAM_XOR9 D Y P2 SRAM_XOR21 D Y P5 D, P Figure 3.14: Write encoder schematic CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 28 3.3.3.3. Parity comparator It could be summarized as following: · P is the XOR operation of all data input bit and parity bit P before being written to memory. · PD is the XOR operation of all data output bit and parity bit P read from memory In which parity bits P are encoded from data input bit Therefore, comparing the P and PD will help determine the error is single or double bit. The comparison of the remain bits indicate the single bit error position PO = XOR{P, PD} Figure 3.15: Parity comparison schematic 3.3.3.4. Syndrome decoder CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 29 Figure 3.16: Syndrome decoder schematic · If PO = 1, single bit error occurred, SE flag will be ON, the FEN signal will be sent to enable the flipping bit task. o If PO=0, the single bit error is one of the parity bit from P0 to P4. The PE flag will be ON o Otherwise, the single bit error is one of the data bit. · If PO = 0 and PO result in a non zero value, then the double bit error occurred, DE flag will be on 3.3.3.5. Bit flipper As can be seen in the table 3.2, any given data bit is included in a unique set of parity bits. Therefore, a 3to8 decoder and a 2to4 decoder are used to decode the comparison bits to find the erroneous bit position. The erroneous bit will be then flipped the state (0 to 1 or 1 to 0) by the bit flipper block. CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 30 3.3.3.6. EDC input/output select and output latch a. Input select RAM_MODE is the EDC block disable pin. If RAM_MODE = 0, the SRAM will work with error detecting and correcting tasks. Otherwise, the SRAM will work in normal mode, without error detecting and correcting tasks. Therefore, during the write operation, RAM_MODE pin acts as the bit write enable pin for six right data input bits. If RAM_MODE = 0, all 22 data bit (16 bit data and 6 bit parity encoded from the write encoder of EDC block) will be written to the memory array. If RAM_MODE = 1, the bit write pin for six right input bits of SRAM is disabled, and only 16 bit data are written BIT FLIPPER 3_DEC_8 P2 P1 P0 PS2 PS1 PS0 PS5 PS4 PS3 PS7 PS6 2_DEC_4 P1 P0 PS2 PS1 PS0 PS3 PO2 PO1 PO0 PO3 PO4 BIT_FLIPPER_0 Q PS1 PS2 FEN DO D FEN D BIT_FLIPPER_15 Q PS1 PS2 FEN DO D FEN D … .. Figure 3.17: Bit flipper block CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 31 to memory array, the six right column of the memory array are then not affected. b. Output select and output latch Each data output bit (QO and notification flags SE, PE, DE) must go through an output select circuit and output latch before going to the output ports. Depending on the RAM_MODE pin status, the output select circuit will select which data can go to the output port. For the notification flags, if RAM_MODE = 1, means no correction tasks occur, all the flags will be tied to VSS. In contrast, when RAM_MODE = 0, the flags will get the value returned from the syndrome decoder block. For the output data, if RAM_MODE = 1, means no correction tasks occurred, the output data will be got directly from the SRAM output. In contrast, when RAM_MODE = 0, the output data is the data which are decoded and corrected. IO cells for six right bits with bitwrite enable pin Figure 3.18: Input select CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 32 Figure 3.19: Output select and output latch All the output bits are also latched by LATCH signal. This LATCH signal is obtained from the output latch signal of SRAM, however, plus a delay to model the delay of data output when passing through the EDC block. This latch is also the hardened latch mentioned in section 3.2.6. Out_latch CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 33 3.4. Physical implementation 3.4.1. Top level design layout view The memory top layout view is partitioned just like the floorplan presented in section 3.1.2. All the input pins are placed at the bottom of the memory. EDC block Memory Array IO Control Xdec RR ee f f ee rr ee nn cc ee ii oo RR ee f f ee rr ee nn cc ee cc oo ll uu mm nn Figure 3.20: Top level layout view CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 34 3.4.2. Memory cell layout Figure 3.21: SRAM cell layout with only device layers shown The SRAM cell has been drawn to minimize the area and try to have smoothly shapes for all layers. There is no strap cell included in SRAM cell to save the area. The strap cell is inserted in each 36 rows. Two SRAM cell will share the same power line. The wordline and protection enable signal are drawn in metal 3 while the bitline signals are drawn in metal 2. This SRAM cell area is 10.35 um2. 3.4.3. Layout view of other block Figure 3.23: Xdec cell layout RWL PENX RB L VS S VD D W BL W BL X Width = 5.75 um, Height = 1.8um, Area = 10.35 (um2) WWL Layer Panel The share power line in m3 Figure 3.22: SRAM cell layout CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 35 Figure 3.24: Xdec array 1x256 Figure 3.25: Control block CHAPTER 3 SOFT ERROR TOLERANT SRAM DESIGN P a g e | 36 Figure 3.26: IO array 1x22 CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 37 CHAPTER 4 DESIGN SIMULATION AND VERIFICATION 4.1. SRAM cell simulation 4.1.1. SRAM cell simulation to find device size To find the best size for the SRAM cell’s transistors, some simulations about read, write current and static noise margin were conducted. 4.1.1.1. Read current (find size of two serial down Nmos N0 and N1) In read operation, the current through the two serial down Nmos is defined as read current. It represents for the speed of read operation. The bigger the read current is, the faster the bit cell can be read. During Read0 operation, there is a current going from RBL through N0 and N1 to ground. It will move the voltage of RBL down. This value must be smaller than the trip-point voltage of the sense inverter during Read0 Operation. During Read1 operation, RBL is not discharged and is kept to ensure V(RBL) is higher than the trip-point voltage of the sense inverter. Therefore, the read current is measured in Read0 operation Measurement method: · Tie IBLX = VDD · Tie RBL = VDD · Sweep V(RWL) from 0 to VDD · Iread = I(N0) when V(RWL) = Figure 4.1: Read current CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 38 VDD Varying the size of N0 and N1 and measuring the read current, we have the following results: Table 4.1: Read current ff -40 1.65 ff 125 1.65 fs 125 1.35 sf 125 1.35 tt 25 1.5 ss 125 1.35 ss -40 1.35 0.3u 155.93 122.64 67.648 49.748 88.844 43.936 54.998 0.45u 219.07 174.89 95.048 72.697 127.35 64.656 80.716 0.6u 283.29 227.99 122.73 95.731 166 85.182 106.12 0.75u 357.9 286.15 157.21 122.57 212.48 109.96 137.36 0.9u 429.84 343.47 190.56 148.72 257.36 134.11 167.46 READ CURRENT (uA)PTV Width N0/N1 To choose the appropriate size for N0 and N1, we must consider the effect of leakage on read current Table 4.2: Read leakage current ff -40 1.65 ff 125 1.65 fs 125 1.35 sf 125 1.35 tt 25 1.5 ss 125 1.35 ss -40 1.35 0.3u 0.76564 871.31 565.89 19.497 0.48766 17.538 0.011769 0.45u 1.1177 891.13 582.29 30.947 0.62219 28.282 0.012704 0.6u 1.4742 1005.5 650.45 42.717 0.77379 38.663 0.013636 0.75u 1.8426 1383.8 894.41 68.68 1.27 62.307 0.014671 0.9u 2.2114 1727 1122.4 95.431 1.7931 86.92 0.015745 LEAKAGE CURRENT (pA) Width N0/N1 PTV Table 4.3: Effect of leakage on read current ff -40 1.65 ff 125 1.65 fs 125 1.35 sf 125 1.35 tt 25 1.5 ss 125 1.35 ss -40 1.35 0.3u 795545.64 549.82 466.96 9967.08 711657.46 9785.89 18254391.83 0.45u 765627.80 766.63 637.62 9176.10 799532.20 8930.15 24818708.67 0.6u 750645.48 885.71 737.05 8754.11 838001.91 8606.22 30399768.99 0.75u 758735.96 807.76 686.60 6971.30 653543.31 6893.79 36573001.16 0.9u 759275.80 776.88 663.20 6087.51 560656.13 6027.00 41545927.28 I_READ/(256*I_LEAK) PTV Width N0/N1 CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 39 The worst case of leakage effect is at fs_125_1.35 because at this corner, the ratio is the smallest comparing with other PTVs. At this PTV, if we vary size of N0/N1, we’ll see that at 0.6u, the ratio is biggest, that mean this size has the minimum effect of leakage compare to other size. Therefore, we chose 0.6u is the size of the two serial down Nmos. 4.1.1.2. Write current During Write0 operation, there is a current going from VDD through PU1 (pull up) and PG1 (pass gate). It will move the voltage of IBL down. This value must be smaller than the trip-point voltage of the feedback inverter to ensure that the value stored in the bit cell can be changed during Write operation. The write current represent for the hard of write operation. The smaller the write current is, the easier the Write operation is Measurement method: · Tie IBLX = 0V, WWL = VDD · Sweep V(WBL) from VDD to 0V · Iwrite = I(PG1) when V(WBL) = 0V Figure 4.2: Write current CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 40 Varying the size of pull up and pass gate transistors, measuring the write current, we have the following results: Table 4.4: Write current PG PU ff -40 1.65 ff 125 1.65 fs 125 1.35 sf 125 1.35 tt 25 1.5 ss 125 1.35 ss -40 1.35 0.15u 51.230 42.797 16.877 24.875 29.023 15.033 16.698 0.16u 53.600 44.862 17.957 26.154 30.587 16.028 17.784 0.17u 55.992 46.936 19.042 27.430 32.162 17.026 18.877 0.18u 58.398 49.015 20.128 28.699 33.744 18.024 19.974 0.19u 60.815 51.096 21.215 29.958 35.331 19.022 21.073 0.2u 63.240 53.176 22.303 31.204 36.919 20.018 22.174 0.15u 51.273 42.849 16.887 24.927 29.050 15.049 16.711 0.16u 53.649 44.921 17.969 26.215 30.618 16.047 17.799 0.17u 56.047 47.002 19.055 27.502 32.197 17.047 18.894 0.18u 58.460 49.090 20.143 28.785 33.784 18.049 19.994 0.19u 60.884 51.180 21.233 30.060 35.375 19.051 21.096 0.2u 63.317 53.271 22.323 31.325 36.970 20.052 22.200 0.15u 51.313 42.896 16.896 24.972 29.074 15.063 16.722 0.16u 53.694 44.973 17.980 26.269 30.645 16.063 17.812 0.17u 56.096 47.061 19.067 27.565 32.228 17.067 18.910 0.18u 58.515 49.156 20.157 28.858 33.819 18.072 20.012 0.19u 60.946 51.255 21.249 30.146 35.416 19.078 21.117 0.2u 63.385 53.355 22.341 31.427 37.015 20.083 22.224 0.15u 51.349 42.938 16.905 25.012 29.096 15.076 16.733 0.16u 53.734 45.021 17.990 26.316 30.670 16.079 17.825 0.17u 56.141 47.115 19.079 27.619 32.257 17.085 18.924 0.18u 58.565 49.216 20.170 28.922 33.851 18.093 20.028 0.19u 61.001 51.322 21.263 30.220 35.452 19.102 21.135 0.2u 63.447 53.431 22.357 31.513 37.055 20.110 22.245 0.15u 51.381 42.975 16.913 25.048 29.115 15.088 16.742 0.16u 53.770 45.063 17.999 26.357 30.693 16.092 17.836 0.17u 56.181 47.163 19.089 27.667 32.282 17.101 18.937 0.18u 58.610 49.270 20.182 28.977 33.880 18.111 20.043 0.19u 61.051 51.383 21.277 30.284 35.484 19.123 21.152 0.2u 63.502 53.498 22.372 31.587 37.092 20.134 22.264 0.15u 51.410 43.010 16.920 25.080 29.133 15.099 16.751 0.16u 53.803 45.102 18.007 26.393 30.713 16.105 17.846 0.17u 56.218 47.206 19.099 27.709 32.305 17.115 18.948 0.18u 58.651 49.319 20.193 29.026 33.906 18.128 20.056 0.19u 61.096 51.437 21.289 30.340 35.513 19.142 21.167 0.2u 63.552 53.558 22.386 31.651 37.125 20.156 22.281 0.19u 0.20u 0.17u 0.18u WRITE CURRENT (uA) 0.15u 0.16u CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 41 4.1.1.3. Static noise margin Static noise margin is an important parameter to evaluate the bitcell's stability. Consider the circuit above, when DC noise source V= 0V, it’s the model of static memory bitcell. If V is big enough, it’ll make the two inverter change state. And from this, static noise margin (SNM) is defined as the maximum DC voltage value of V that the 2 inverters can endure to keep their logical values. Varying the size of pull up and pull down transistors, we run simulation to measure the SNM for this SRAM cell. Table 4.5: Static noise margin PD PU ff -40 1.65 ff 125 1.65 fs 125 1.35 sf 125 1.35 tt 25 1.5 ss 125 1.35 ss -40 1.35 0.15u 0.3430 0.2578 0.2046 0.3237 0.3316 0.3020 0.3345 0.16u 0.3452 0.2618 0.2081 0.3254 0.3336 0.3045 0.3359 0.17u 0.3474 0.2656 0.2114 0.3271 0.3356 0.3068 0.3371 0.18u 0.3495 0.2693 0.2146 0.3288 0.3375 0.3090 0.3383 0.19u 0.3515 0.2728 0.2176 0.3303 0.3393 0.3111 0.3395 0.2u 0.3535 0.2762 0.2205 0.3318 0.3411 0.3130 0.3405 0.15u 0.3811 0.2917 0.2351 0.3398 0.3594 0.3210 0.3484 0.16u 0.3831 0.2952 0.2384 0.3415 0.3613 0.3234 0.3498 0.17u 0.3850 0.2986 0.2415 0.3431 0.3632 0.3257 0.3510 0.18u 0.3868 0.3020 0.2444 0.3446 0.3649 0.3278 0.3520 0.19u 0.3886 0.3051 0.2472 0.3461 0.3665 0.3297 0.3529 0.2u 0.3904 0.3082 0.2498 0.3475 0.3682 0.3315 0.3538 STATIC NOISE MARGIN 0.15 0.20u low I1 I2 high high low + V - + V - CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 42 0.15u 0.4004 0.3087 0.2499 0.3490 0.3738 0.3315 0.3574 0.16u 0.4023 0.3121 0.2532 0.3507 0.3758 0.3339 0.3585 0.17u 0.4041 0.3154 0.2562 0.3523 0.3776 0.3360 0.3597 0.18u 0.4058 0.3185 0.2590 0.3539 0.3793 0.3381 0.3608 0.19u 0.4075 0.3215 0.2617 0.3553 0.3809 0.3401 0.3618 0.2u 0.4092 0.3244 0.2642 0.3566 0.3824 0.3419 0.3626 0.15u 0.4074 0.3149 0.2553 0.3526 0.3792 0.3354 0.3611 0.16u 0.4092 0.3182 0.2585 0.3543 0.3811 0.3378 0.3622 0.17u 0.4110 0.3215 0.2615 0.3558 0.3829 0.3400 0.3632 0.18u 0.4127 0.3245 0.2643 0.3574 0.3846 0.3420 0.3643 0.19u 0.4144 0.3275 0.2669 0.3588 0.3862 0.3439 0.3652 0.2u 0.4161 0.3303 0.2694 0.3602 0.3878 0.3458 0.3661 0.15u 0.4267 0.3319 0.2700 0.3629 0.3943 0.3466 0.3719 0.16u 0.4285 0.3351 0.2732 0.3646 0.3961 0.3490 0.3730 0.17u 0.4303 0.3382 0.2761 0.3662 0.3979 0.3512 0.3740 0.18u 0.4319 0.3411 0.2789 0.3677 0.3997 0.3533 0.3749 0.19u 0.4336 0.3440 0.2815 0.3691 0.4013 0.3552 0.3757 0.2u 0.4351 0.3467 0.2839 0.3704 0.4028 0.3570 0.3765 0.25u 0.3u 0.235u Through the simulation results about write current and static noise margin, we could choose the appropriate size for PG, PU, PD transistor. To archive the small write current, the PU and PG transistor should be chosen with small width. 0.15u is the smallest, however to obtain a better SNM, the 0.16u will be the decision. The PD transistor was chosen based on the desired SNM. As can be seen from table 4.5, the bigger width of PD transistor, the better SNM it gets. However, this will be traded off with the SRAM cell area. Therefore, 0.235u was chosen to get the SNM about 0.4. 4.1.2. SRAM cell characteristic summary The table 4.6 below summarizes the characteristic of SRAM cell with fixed size of transistors CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 43 Table 4.6: SRAM cell characteristic summary SRAM CELL CHARACTERISTIC PTV iread (uA) iwrite (uA) SNM ileak read (pA) ileak total (pA) ss_125_1.35 85.182 16.047 0.334 38.663 65.377 ss_-40_1.35 106.120 17.799 0.359 0.014 0.127 ff_-40_1.65 283.290 53.649 0.402 1.474 7.195 ff_125_1.65 227.990 44.921 0.312 1005.500 2915.000 tt_25_1.5 166.000 30.618 0.376 0.774 2.294 fs_125_1.35 122.730 17.969 0.253 650.450 1900.500 sf_125_1.35 95.731 26.215 0.351 42.717 72.761 4.1.3. Static noise margin comparison A static noise margin simulation was also conducted on the normal 8T SRAM cell to see the difference with the hardened 8T SRAM cell. Obviously, the hardened SRAM cell has the bigger SNM in all PTVs (about 1.5 times). This proves that the hardened SRAM cell has the higher stability than the normal 8T SRAM cell. Table 4.7: SNM comparison SNM COMPARISON SRAM cell type ff-40 1.65 ff 125 1.65 fs 125 1.35 sf 125 1.35 tt 25 1.5 ss 125 1.35 ss-40 1.35 Normal 8T SRAM cell 0.2823 0.2215 0.1794 0.2844 0.2812 0.2617 0.3008 Hardened SRAM cell 0.402 0.312 0.253 0.351 0.376 0.334 0.359 4.1.4. SRAM cell capacitance The table 4.8 below shows the capacitance value of the signals in SRAM cell. CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 44 Table 4. 8: SRAM cell capacitance Total Capacitance (fF) Signal Name Max Typ Min RBL 0.5414 0.5149 0.4904 WBLX 0.6703 0.6368 0.6049 WBL 0.7701 0.7289 0.6902 RWL 1.4668 1.3958 1.3284 WWL 1.2814 1.2235 1.1694 PENX 1.6804 1.599 1.5209 4.2. Soft error tolerant simulation To verify the tolerant level of the SRAM cell, a critical charge simulation was carried out to measure the critical charge of normal 8T SRAM cell and the harden 8T SRAM cell in this design. 4.2.1. Verification methodology The region that is most sensitive to ion strikes are reverse-biased junctions, because of the electric field present across the large space charge region, hence efficiently collecting any charge generated in their vicinity. In the 8T SRAM designs, the off-NMOS drain is the most sensitive region of the cell (in addition to the off-PMOS) as mentioned in section 2.2. To measure the critical charge for 8T SRAM cell, a current source will be injected to the off NMOS drain [14, 15], applied across the drain terminal and the ground as in figure 4.3 below A radiation particle strike can be modeled by a current pulse as (4.1) where: Qcoll is the amount of charge collected )( )( )( // ba tt ba tt ttcoll seu ee Q ti -- - - = CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 45 tα is the collection time constant. tβ is the ion track establishment constant The time constants tα and tβ depend upon process related parameters. For each technology, we must determine (tα, tβ) to make sure the current model that we used is correct. In this 130nm process, tα is 164 ps and tβ is 50 ps Figure 4.3: Inject a current source to an off NMOS drain 4.2.2. Critical charge simulation Iseut CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 46 · Define the following line in the spice deck file to insert the current pulse iseu xi0.ibl 0 PWL (time,'((charge/(tanpha-tbeta))*((exp((tdelay- value)/tanpha))-exp((tdelay-value)/tbeta)))') This is the same equation with the equation 4.1, but in the correct syntax that Hspice can understand · Initialize: o V(IBL) = VDD o V(IBLX) = 0 o V(WWL) = V(RWL) = 0 o V(RBL) = V(WBL) = V(WBLX) = 1 · Using Hspice to transient analyze with data that was generated from iseu(t) · Varying Q to determine the maximum of Q automatically when the stored data flip, that Q is called critical charge (Qcrit). 4.2.3. Simulation results 4.2.3.1. Hardened SRAM cell Table 4.9: Critical charge result of hardened SRAM cell Hardened SRAM cell RC condition Critical charge (fC) FF_-40_1.65 16.4062 TT_25_1.5 11.5019 SS_125_1.35 6.2705 CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 47 Figure 4.4: The injected SEU current for hardened SRAM cell Figure 4.5: IBL waveform of hardened SRAM cell Figure 4.6: The exchange state between IBL and IBLX 4.2.3.2. Normal SRAM cell Q= 3 fC Q= 6 fC Q= 9 fC Q= 11.502 fC Q= 3 fC Q= 6 fC Q= 9 fC Q= 11.502 fC IBL flip when Q= 11.502 fC TYPICAL CONDITION TYPICAL CONDITION IBLX IBL TYPICAL CONDITION CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 48 Table 4.10: Critical charge result for normal SRAM cell Normal SRAM cell RC condition Critical charge (fC) FF_-40_1.65 8.8945 TT_25_1.5 6.2167 SS_125_1.35 4.5329 Figure 4.7: The injected SEU current for normal SRAM cell Figure 4.8: IBL waveform of normal SRAM cell TYPICAL CONDITION Q= 1.5 fC Q= 3 fC Q= 4.5 fC Q= 6.217 fC Q= 1.5 fC Q= 3 fC Q= 4.5 fC Q= 6.217 fC IBL flip when Q= 6.217 fC TYPICAL CONDITION CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 49 Figure 4.9: The exchange state between IBL and IBLX 4.2.4. Conclusion By injecting the same current pulse to both SRAM cell, varying the charge and transient analysis, we found the critical charge for hardened SRAM cell and normal SRAM cell. As the result, the SRAM cell which used circuit hardening techniques has the larger critical charge value in all RC condition, which means it has the higher tolerant level compare with normal 8TSRAM cell. TYPICAL CONDITION CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 50 4.3. Post-layout simulation After finishing the physical implementation for the design, a layout parasitic extracted (LPE) netlist is extracted and then is used to simulate to evaluate the performance of the design. The simulations were conducted to measure the cycle time, access time, setup time and the delay of some critical paths. 4.3.1. Simulation setup Hspice was invoked to run the simulation. The necessary data for this simulation includes: · LPE netlist The LPE netlist contains the connectivity of the design, also the full resistor and capacitor information. Figure 4.10: A part of LPE netlist containing capacitor value CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 51 Figure 4.11: A part of LPE netlist containing resistor value · Input waveform To model the worst case and to save the runtime, only the furthest row (max address) will be written and read. Figure 4.12: A part of input waveform for performance simulation CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 52 · Spice option This file contains the Hsim option, the paths to necessary data, path to model file and defines some necessary parameters Figure 4.13: Hspice option 4.3.2. Cycle time definition and simulation result The cycle time is the minimum period that CLK could be activated again and make sure that the design has been reset and ready for new data. Cycle time must cover all below conditions: · Covering the cycle of internal clock and be ready for starting new cycle CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 53 CYCLE1 = CLK rise to RESETX rise 90%VDD From the simulation output waveform, measuring the delay from clk rise to resetx rise 80%VDD, we obtained the CYCLE1 = 4.15 ns Figure 4.15: Delay from clk rise to resetx rise · Make sure all RBL be pre-charged fully CLK LCP RCP ECHO HCPFB RESET RESETX CYCLE 1 Figure 4.14: Cycle time must cover the internal clock CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 54 CYCLE2 = CLKA rising-to-DMRBL rising to 90% of VDD From the simulation output waveform, measuring the delay from clk rise to dmrbl rise 90%VDD, we obtained the CYCLE2 = 4.93 ns Figure 4.17: Delay from clk rise to dmrbl rise · Cover the pulse width high of input latch (from latch close to latch open again) plus to max setup time of all input pins CLKA INTCLKX RHCPX RBL CYCLE 2 Figure 4.16: Cycle time must make sure all RBL be precharged fully CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 55 Figure 4.18: Cycle time must cover PWH of input latch plus for max setup time CYCLE3 = PWH {LATCLK} + Setup_max {Input pin/bus} From the simulation output waveform, we got the pulse width high of latch is 3.53 ns, plus for the max setup time 385ps, we obtained CYCLE3 = 3.915ns Figure 4.19: PWH of input latch The cycle time for this design is the maximum value of the CYCLE1, CYCLE2, CYCLE3. Therefore: CYCLE = max{CYCLE1, CYCLE2, CYCLE3} = max {4.15ns, 4.93ns, 3.915ns} = 4.93ns 4.3.3. Access time CYCLE 3 CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 56 Access time is maximum delay from clock to output validation. Figure 4.20: Access time definition The access time measured from output waveform has the value 4.22 ns. This is the delay from the rising edge of clk to the rising edge of the furthest data output Figure 4.21:Access time 4.3.4. Setup time Setup time is a minimum period that the signal must be valid before the activation of CLK. Setup time is measured for all input signals. In this design, the max measured setup time is the setup time of address signals. The setup time of address input is measured as below: SETUP_TIME = address_input_path_delay - clock_path_delay In which D_OUT valid CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 57 · The address_input_path_delay is the delay from the rising edge of address signal to the falling edge of node dx1 in the input latch (the period for address signal to travel to input latch) · The clock_path_delay is the delay from the rising edge of clock to the rising edge of latch signal (the period for clock to active the latch signal to open input latch) The equation to measure setup time is given based on the worst case: input latch opens at the same time when input data arrives. Therefore, the difference between these two delays will determine the minimum period that the signal must be valid before clock. The figure 4.22 and 4.23 below show the delay of address_input_path_delay and clock_path_delay Figure 4.22: Address input path delay Figure 4.23: Clock path delay From the simulation result, we got the max setup time is: 735-350 = 385 ps 4.3.5. Timing delay of some critical paths CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 58 · Delay from CLKA rises to intclkx fall: delay from external clock to internal clock generation Figure 4.24: Delay from CLKA to intckx fall · Delay from intclkx fall to rhcpx fall: the period in which read internal clock are sent to IO to start the read operation Figure 4.25: Delay from intclk fall to rhcpx fall · Delay from rhcpx fall to latch rise: the period from internal read clock active to data output latch open · Delay from rhcpx fall to echo rise: the period from internal read clock active to echo active to be sent back to reset internal clock Figure 4.26: Delay from rhcpx fall to latch rise CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 59 Figure 4. 27: Delay from rhcpx fall to echo rise · Delay from echo rise to resetx fall: the period from echo active to reset active Figure 4.28: Delay from echo rise to resetx fall · Delay from resetx fall to intclk rise: the period from reset active to internal clock disable Figure 4.29: Delay from resetx fall to intclk rise · Delay from intclk rise to rhcpx rise: disable clock is sent to IO CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 60 Figure 4.30: delay from intclk rise to rhcpx rise · Delay from rhcpx rise to latch fall: period from internal clock is reset to output latch is closed Figure 4.31: Delay from rhcpx rise to latch fall · Delay from intclk rise to resetx rise: reset signal is disabled to start a new read cycle Figure 4.32: Delay from intclk rise to resetx rise CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 61 4.3.6. Simulation results summary 4.3.6.1. Performance Table 4.11: Performance result (SS_125_1.35) Parameters Description Value (ns) Cycle time Clock cycle time 4.93 Access time Clock high to read data valid 4.22 Setup time Max input setup time 0.385 4.3.6.2. Timing delay of some critical paths Table 4.12: Timing delay between nodes Timing delay between nodes Delay Timing Between Nodes Value (ns) Description CLKA rise -- intclkx fall 0.167 Generate internal clock intclkx fall -- rhcpx fall 0.232 Internal clock is sent to IO rhcpx fall -- latch rise 3.31 Open output latch rhcpx fall -- echo rise 3.16 Send echo signal back echo rise -- resetx fall 0.093 Echo signal enables the reset signal resetx fall -- intclkx rise 0.112 Reset signal will reset internal clock intclkx rise -- rhcpx rise 0.2 Reset internal clock will be sent to IO rhcpx rise -- latch fall 0.688 Close the output latch Intclkx rise -- resetx rise 0.354 Off reset to start a new cycle 4.4. SRAM and EDC functional verification CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 62 To verify to functional of this design, firstly we must define a set of test vectors which can cover all possible faults such as: cannot read/write, cannot operate the detection and correction task.... Then, Hsim jobs are conducted to simulate for all test cases. With input are the test vectors, we will expect the correct output data. If all data output are as expected then the design functional are correct. 4.4.1. Fault model The test vectors must be defined to cover all possible faults as below: Table 4.13: Design fault model # Item Fault 1 SRAM function 1.1 Cannot store a value in each SRAM cell 1.2 Cannot write/read in each SRAM cell 1.3 A certain address results in no cell accessed 1.4 A certain address accesses multiple cells 1.5 A certain cell can be accessed by multiple addresses 2 EDC function 2.1 Cannot encode the input data to parity bit 2.2 Cannot decode the output data to check bit 2.3 Cannot detect single bit or double bit error 2.4 Cannot fix single bit error 4.4.2. Test vector definition 4.4.2.1. Vector sram_00_01 CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 63 · Purpose: Test the write/read operation of SRAM · Cover fault model: all SRAM function fault model · Description: This test vector includes checking for the write and read operation. First, write 0 to all word, and then read 0 at the max word. After that, we write 1 and read 0 simultaneously at two adjacent addresses, from max word to min word. For example, write 1 at word 255th and read 0 at word 254th, then write 1 at word 254th and read 0 at word 253th, then continue to the min word. Similarly for case write 1 but with the invert direction from min word to max word. This method can cover all possible faults of SRAM functionality such as: a certain address accesses multiple cell, a certain address accesses no cell, cannot read/write from SRAM... The detail vector is as following: 4.4.2.2. Vector sram_00_02 · Purpose: Test the ability to detect and correct error of EDC block > For AB in 0 . . nw1 + write 0 > For AA = nw1 + read 0 > For AB in nw1..1 (step 1), AA = AB - 1 + write 1, read 0 > For AB = 0 + write 1 > For AA = 0 + read 1 > For AB = 0..(nw-2), AA = AB + 1 + write 0, read 1 CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 64 · Cover fault model: all EDC function fault model · Description: The function of EDC block can be done by first writing the correct data to the memory with RAM_MODE=0, then write the incorrect data to the memory with RAM_MODE =1 (the six left parity bits are not affected). Then read with RAM_MODE=0 to check whether the incorrect bit is fixed. The pattern would be defined to check for all bit error positions. The detail vector is as following: > AB = 0, RAM_MODE = 0 + write 0 > AA = 0, RAM_MODE = 0 + read 0 > AB = 0, RAM_MODE =1 + write 10000000000000 > AA = 0, RAM_MODE =1 + read 100000000000000 > AA = 0, RAM_MODE = 0 + read 0 + SE flag is ON (The data has been fixed) .... Continue to write incorrect data with changing the incorrect bit 1 position and read the fixed data to test the ability to detect and correct all bit position... CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 65 4.4.3. Simulation setup > AB = 0, RAM_MODE = 0 + write 1 > AA = 0, RAM_MODE = 0 + read 1 > AB = 0, RAM_MODE =1 + write 0111111111111111 > AA = 0, RAM_MODE =1 + read 01111111111111111 > AA = 0, RAM_MODE = 0 + read 1 + SE flag is on (The data has been fixed) .... Continue to write incorrect data with changing the incorrect bit 0 position and read the fixed data to test the ability to detect and correct all bit position... > AB = 0, RAM_MODE = 0 + write 1 > AA = 0, RAM_MODE = 0 + read 1 > AB = 0, RAM_MODE =1 + write 0011111111111111 > AA = 0, RAM_MODE =1 + read 00111111111111111 > AA = 0, RAM_MODE = 0 + read 00111111111111111 + DE flag is on .... Continue to write incorrect data with changing the incorrect double bit 00 positions to test the ability to detect double bit error. CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 66 To run Hsim simulation, some below data must be prepared: · Netlist of full design Figure 4.33: Netlist of top level · Full vectors as described above in section 4.4.2 Figure 4.34: A part of full test vector · The spice setup file which contains the Hsim option, the paths to necessary data, path to model file, some necessary parameters... CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 67 Figure 4.35: Hsim option After preparing all necessary data, invoke the Hsim command to run simulation for two defined test vectors. 4.4.4. Functional verification result All the output data are as expected and no error is produced. Below is the simulation log file: path_to_model_file CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 68 The simulation waveform for test vector sram_00_01 is shown in figure 4.37 below. Because the full waveform is too large, this figure only captured one part of the full waveform. Figure 4.37: Waveform of SRAM functional simulation Figure 4.36: Hsim log file CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 69 The simulation waveform for test vector sram_00_02 is shown in figure 4.38 below. The waveform in figure below only captured the error at max significant bit. Figure 4.38: Waveform of EDC functional simulation CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 70 4.5. Physical verification The physical verification for this design includes LVS (layout versus schematic) and DRC (design rule check) verification. The Calibre tool was used to perform LVS and DRC checking for the design. Figure 4.23 below shows the LVS report of a hierarchical checking from top level. CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 71 Figure 4.39: LVS Calibre report for hierachical checking As can be seen from figure 4.23, all layout cells has passed the LVS checking The next figure 4.24 also show the detail LVS report for top cell ecc_chip. The report list the mapping of ports and nets between layout and schematic. CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 72 Figure 4.40: Detail LVS report for top level CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 73 Figure 4.25 shows the DRC report for this design. The report contains the design rule check information and list the total result count for each checking. As shown in the report, there are no DRC errors. The design has passed the DRC verification by Calibre tool CHAPTER 4 DESIGN SIMULATION AND VERIFICATION P a g e | 74 Figure 4.41: DRC report CHAPTER 5 CONCLUSION AND FUTURE WORK P a g e | 75 CHAPTER 5 CONCLUSION AND FUTURE WORK A 1Kx22 bits SRAM chip was designed and simulated in 130nm CMOS technology. This SRAM has the additional soft error tolerant level. The critical charge simulation results indicated that the hardened SRAM cell has the higher tolerant level than the normal SRAM cell. The functional verification for SRAM and EDC block also demonstrated the correct functionality of the design and the ability to detect and correct single bit error of EDC block. The performance of the design was also evaluated through the post layout simulation. With the soft error tolerant feature, this SRAM design could be used for the applications which required the high reliability functionality. However, the two techniques that were applied for this design also cause the area and performance overhead. The radiation technique requires adding extra transistors; therefore it leads to increase the area. The timing is also affected by the built-in EDC block. For instances, the access time has increased because the data output from SRAM must be processed by the EDC block to detect and correct error before coming to the output ports. Beside some drawbacks, this thesis has finished well a SRAM design which can be applied for some critical applications. This SRAM is still need to be developed. Some more work should be invoked to study how to minimize the effect on area and timing. For example, study to reduce the extra transistors in the hardened SRAM cell architecture or in the latches, also optimize the EDC architecture to obtain a better timing. REFERENCES P a g e | 76 REFERENCES [1] R. Baumann, "Soft Errors In Commercial Integration Integrated Circuits," International Jour. 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